1. Field of the Invention
The present invention relates to determination of critical area and, more particularly, to a method and system for computing critical areas for predicting yield for semiconductor devices.
2. Description of the Related Art
Critical area of a very large scale integration (VLSI) layout is a measure that reflects the sensitivity of the layout to defects occurring during the manufacturing process. Critical area is widely used to predict the yield of a VLSI chip. Yield prediction is essential in today's VLSI manufacturing due to the growing need to control cost. Models for yield estimation are based on the concept of critical area which represents the main computational problem in the analysis of yield loss due to spot defects during fabrication. Spot defects are caused by particles such as dust and other contaminants in materials and equipment and are classified into two types: "extra material" defects causing shorts between different conducting regions and "missing material" defects causing open circuits.
Extra material defects appear most frequently in a typical manufacturing process and are the main reason for yield loss. The yield of a chip, denoted by Y, is computed as ##EQU1##
where Yi is the yield associated with the ith step of the manufacturing process. The yield of a single processing step is modeled as ##EQU2##
where d denotes the average number of defects per unit of area, a the clustering parameter, and A.sub.c, the critical area.
For a circuit layout C, the critical area is defined as ##EQU3##
where A(r) denotes the area in which the center of a defect of radius r must fall in order to cause circuit failure and D(r) is the density function of the defect size. The defect density function has been estimated as follows: ##EQU4##
where p, q are real numbers (typically p 3, q=1), c=(q+1)(p-1)(q+p), and r.sub.0 is some minimum optically resolvable size.
Existing methods for yield prediction and critical area computation can be classified into the following types:
1. Geometric methods: Compute A(r) for several different values of r independently. Use the results to approximate A.sub.c. The methods to compute A(r) are usually based on shape-expansion followed by shape-intersection (see e.g., S. Gandemer et al., "Critical Area and critical levels calculation in IC yield modeling", IEEE J. of Solid State Circuits, vol.35, No 2, February 1988, 158-166.) and have a quadratic flavor. For rectilinear layouts there is also a scan-line method which computes critical areas in multiple layers. (see e.g. J. Pineda de Gyvez, C. Di, "IC Defect Sensitivity for Footprint-Type Spot Defects", IEEE Trans. on Computer-Aided Design, vol. 11, no 5, 638-658, May 1992)
2. Virtual artwork approach: Build a virtual artwork having the same statistical features as the nominal IC layout. The virtual artwork is arranged in a form allowing easy calculation of the critical area as a function of the defect radius (see e.g., W. Maly, "Modeling of lithography related yield losses for CAD of VLSI circuits" IEEE Transactions on Computer-Aided Design, vol. CAD-4, no 3, 166-177, July 1985.). Accuracy is limited by differences in the detail of the nominal and virtual artworks.
3. Monte Carlo approach: Draw a large number of defects with their radii distributed according to D(r), check for each defect if it causes a fault, and divide the number of defects causing faults over the total number of defects. (See e.g., H. Walker and S. W. Director, "VLASIC: A yield simulator for integrated circuits", IEEE Trans. on Computer-Aided Design, vol. CAD-5, no 4, 541-556, October 1986.)
4. Grid approach: Assume an integer grid over the layout. Compute the critical radius (the radius of the smallest defect causing a fault at this point) for every grid point (see e.g., I. A. Wagner and 1. Koren, "An Interactive VLSI CAD Tool for Yield Estimation", IEEE Trans. on Semiconductor Manufacturing Vol. 8, No.2, 1995, 130-138). The method works in O(I.sup.1.5) time, where I is the number of grid points. The accuracy depends on the density of the grid.
The above approaches suffer from accuracy and complexity problems as described. Therefore, a need exists for an improved approach for computing the critical area for shorts in a single layer of a semiconductor device. A further need exists for a low polynomial algorithm for computing critical area for shorts with improved accurately and reduced complexity.